1. Field of the Invention
The present invention relates to a row decoder circuit in a flash memory device which can increase the number of a local row decoder, to which an output of a global row decoder is input, as many number of sectors when the sectors are divided in a column direction.
2. Description of the Prior Art
Generally, a flash memory device has both functions of electrical program and erasure. In the flash memory device capable of programming sector-by-sector, it is a general requirement that the write cycle of more than a hundred thousand has to be guaranteed. At this time, the number of stress acted to the gate of unit cell is same as the number of the unit cell connected to a single word line, and the number of stress acted to the drain of unit cell is same as the number of the unit cell connected to a single bit line.
FIG. 1 is a circuit diagram of a conventional row decoder.
In a read mode, a first voltage supply signal SnVppx of a selected sector is switched to a Vdd voltage level and a second voltage supply signals SnVeex and XRST thereof are switched to a ground voltage level. At this time, as a PMOS transistor hp1 is turned on, a node A has a Vdd voltage level and the Vdd voltage level of the node A turns on a NMOS transistor thn, thus a sector word line signal SnWL maintains a ground voltage level.
On the other hand, one XNCOM selected by a NAND gate I to which row address signals XBPRED and XCPRED and a sector signal S are input maintains a ground voltage level. At this time, since only a single XAPRED maintains a Vdd voltage level, a NMOS transistor hn of the row decoder which will be selected is turned on, the node A of the selected row decoder maintains a ground voltage level. Therefore, the ground voltage level applied to the node A causes a PMOS transistor hp3 to turn on, thus a sector word line signal SnWL maintains a Vpp voltage level.
In a program mode, the first voltage supply signal SnVppx of the selected sector is switched to a Vpp voltage level, the second voltage supply signal SnVeex thereof is switched to a ground voltage level. The XRST thereof maintains a ground voltage level before the first voltage supply signal SnVppx is switched to Vpp voltage and is switched to Vpp voltage level when the first voltage supply signal SnVppx is switched to Vpp voltage. A first voltage supply signal SnVppx of a non-selected sector maintains a Vdd voltage level and the XRST of the non-selected sector maintains a ground voltage level so that a word line SnWL of the not-selected sector is switched to a ground voltage level.
On the other hand, one XnCOM selected by a NAND gate I to which row address signals XBPRED and XCPRED and the sector signal S are input maintains a ground voltage level. At this time, since only a single XAPRED maintains a Vdd voltage level, a NMOS transistor hn of the row decoder which will be selected is turned on, the node A of the selected row decoder maintains a ground voltage level. Therefore, the ground voltage level applied to the node A causes a PMOS transistor hp3 to turn on, thus a sector word line signal SnWL maintains a Vpp voltage level.
In an erase mode, the first voltage supply signal SnVppx of the selected sector is switched to a ground voltage level, the second voltage supply signal SnVeex thereof is switched to a −Vpp voltage level, and XRST thereof is switched to a ground voltage level. And, a first voltage supply signal SnVppx of a non-selected sector is switched to a Vdd voltage level, a second voltage supply signal SnVeex thereof is switched to a ground voltage level, and the XRST thereof is switched to a ground voltage level.
As a result, as the node A of the non-selected sector is at Vdd voltage level, the sector word line thereof maintains a ground voltage level. Meanwhile, as the NMOS transistor thn in the row decoder of the selected sector is turned on, all the word line signals SnWL maintain a −Vpp voltage level.
In the row decoder as described above, the number of the row decoder is increased as many when the sector is divided in a column direction, the number of XnCOM of the row decoder is increased. Therefore, a free decoder output load and an address buffer output load are increased proportionally. As a result, an access time is delayed and the size of a chip becomes large.